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â Wide/Narrow Switching Circuit
The Wide port (pin 65) and Narrow port (pin 64) of the CPU is used to switch between ceramic filters. When the Wide port is high, the ceramic filter SW diodes (D303, D302) cause CF301 to turn on to receive a Wide signal. When the Narrow port is high, the ceramic filter SW diodes (D303, D302) cause CF302 to turn on to receive a Narrow signal. (See Fig. 3.)
â Squelch Circuit
The detection output from the FM IF IC (IC301) passes through a noise amplifier (Q301) to detect noise. A voltage is applied to the CPU (IC101). The CPU controls squelch according to the voltage (SQIN) level. The signal from the RSSI pin of IC301 is used for S-meter. The electric field strength of the receive signal can be known before the SQIN voltage is input to the CPU, and the scan stop speed is improved.
IC301 AFO IF SYSTEM RSSI Q301 NOISE AMP D301 SQIN DET CPU RSSI IC101
IC301 IF System R318
Wide IC101 65pin R317
Fig. 5 Squelch circuit
PLL Frequency Synthesizer
The PLL circuit generates the first local oscillator signal for reception and the RF signal for transmission.
Narrow IC101 64pin
Fig. 3 Wide/Narrow switching circuit â AF Signal System
The detection signal from IF IC (IC301) goes to D/A converter (IC161) to adjust the gain and is output to AF filter (IC251) for characterizing the signal. The AF signal output from IC251 and the DTMF signal, BEEP signal are summed and the resulting signal goes to the D/A converter (IC161). The AFO output level is adjusted by the D/A converter. The signal output from the D/A converter is input to the audio power amplifier (IC252). The AF signal from IC252 switches between the internal speaker and speaker jack (J1) output. (See Fig. 4.)
IC301 IF IC IC161 W/NO D/A (EVOL2) CONV. IC251 AF Filter IC161 D/A CONV. IC252 AF PA SP
The frequency step of the PLL circuit is 5 or 6.25kHz. A 16.8MHz reference oscillator signal is divided at IC401 by a fixed counter to produce the 5 or 6.25kHz reference frequency. The voltage controlled oscillator (VCO) output signal is buffer amplified by Q410, then divided in IC401 by a dualmodule programmable counter. The divided signal is compared in phase with the 5 or 6.25kHz reference signal in the phase comparator in IC401. The output signal from the phase comparator is filtered through a low-pass filter and passed to the VCO to control the oscillator frequency. (See Fig. 6)
The operating frequency is generated by Q406 in transmit mode and Q405 in receive mode. The oscillator frequency is controlled by applying the VCO control voltage, obtained from the phase comparator, to the varactor diodes (D405 and D406 in transmit mode and D403 and D404 in receive mode). The TX/RX pin is set high in receive mode causing Q408 and Q407 to turn Q406 off, and turn Q405 on. The TX/RX pin is set low in transmit mode. The outputs from Q405 and Q406 are amplified by Q410 and sent to the RF amplifiers. (See Fig. 6.)
AF signal system
IC401 : PLL IC 5kHz/6.25kHz 1/N Q402,403 PLL DATA REF OSC 1/M 5kHz/6.25kHz D403,404 Phase comparator Charge pump LPF D405,406 Q405 RX VCO Q407,408 T/R SW TX/RX (CPU) RF amplifiers Q406 TX VCO Q410 BUFF AMP Q404 AMP
Fig. 6 PLL circuit